Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequenceshave more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flopsresults more power dissipation. To overcome this problem, one method is to use GA to have test vectors of...

Optimization Techniques for Low Power VLSI Circuits

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Low Power Testing of VLSI Circuits: Problems and Solutions

Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to the circuit reliability. Moreover, it may be responsible for cost, performance verification as well as technology related problems and can dramatically shorten the battery life when on-line testing is considered. In th...

Power Electronic Circuits Design: A Particle Swarm Optimization Approach

The development of power electronics results in a growing need for automatic design and optimization for power electronic circuits (PECs). This paper presents a particle swarm optimization (PSO) approach for the PECs design. The optimization problem is divided into two processes using a decoupled technique and PSO is employed to optimize the values of the circuit components in the power convers...